1. Field of the Invention
The present invention relates to a section selecting loop filter and a phase locked loop circuit having the same.
2. Description of the Related Art
A phase locked loop (hereinafter, referred to as “PLL”) circuit synchronizes the phase of a local signal with a reference signal. Generally, the local signal is used in a clock recovery circuit of a digital communication system, a frequency synthesizer, and as a clock generator of a microprocessor and a modulation-demodulation circuit, etc.
FIG. 1 is a block diagram illustrating the architecture of a general phase locked loop circuit.
As shown in FIG. 1, the PLL circuit generally includes a phase detector 100, a charge pump 110, a loop filter 120 and a voltage controlled oscillator 130.
The phase detector 100 detects the difference in phase between a reference signal and a local signal provided from the voltage controlled oscillator 130, and outputs a pulse signal in accordance with the result of the detection. The charge pump 110 outputs a current in accordance with the pulse signal provided from the phase detector 100. The loop filter 120 outputs a tuning signal having a tuning voltage in accordance with the current provided from the charge pump 110 to the voltage controlled oscillator 130. The voltage controlled oscillator 130 outputs the local signal in accordance with the tuning signal provided from the loop filter 120.
The loop filter 120 generates the tuning signal in accordance with the current provided from the charge pump 110. In addition, the loop filter 120 filters noise from the current provided from the charge pump 110 to remove a noise.
The conventional loop filter 120 includes two MiM (metal insulator metals) capacitors (C1, C2) and a resistor (R1) as shown in FIG. 2.
The loop filter mentioned above is typically disposed in an integrated circuit. The loop filter includes a capacitor and the capacitor that occupies a small area per unit capacitance is needed to reduce the overall size of the loop filter. However, it is difficult to reduce the area occupied by the capacitor1 in the loop filter because the MiM capacitors generally used in CMOS processes have low capacitance per unit capacitor.
A MiM capacitor forms one of the two electric nodes between one metal and another metal to increase the capacitance, and an extra mask is required.
Alternatively, a MOS capacitor instead of a CMOS capacitor can be used. A MOS capacitor has high capacitance and does not require an extra mask. For example, while capacitance per unit area of the MiM capacitor used in 0.18 μm CMOS process is 1 μF/μm2, capacitance per unit area of the MOS capacitor is 8 μF/μm2.
FIG. 3A shows a conventional loop filter using a NMOS capacitor, and FIG. 3B shows another conventional loop filter using a PMOS capacitor.
As shown in FIG. 3A, the loop filter includes a first NMOS capacitor (NMC1) and a second NMOS capacitor (NMC2) coupled in parallel and a resistor (R2) coupled in series to the first NMOS capacitor (NMC1). The first NMOS capacitor (NMC1) and the second NMOS capacitor (NMC2) are operated only when the voltage of a gate of the NMOS is above the threshold voltage (VTN) of the NMOS capacitor.
As shown in FIG. 3B, the loop filter includes a first PMOS capacitor (PMC1) and a second PMOS capacitor (PMC2) coupled in parallel and a resistor (R3) coupled in series to the first PMOS capacitor (PMC1). Here, the first PMOS capacitor (PMC1) and the second PMOS capacitor (PMC2) are operated only when the voltage of a gate of the PMOS is at voltages below a bias voltage (Vdd) minus a threshold voltage (VTP) of the PMOS capacitor.
The loop filter as shown above includes a NMOS capacitor and a PMOS capacitor.
In the case of a loop filter including a NMOS capacitor, the loop filter is not operated when the voltage of the gate is not more than the threshold voltage (VTN) of the NMOS capacitor. Whereas in the case of a loop filter including a PMOS capacitor, the loop filter is not operated when the voltage of the gate is above a voltage that equals to the bias voltage ( Vdd) minus the threshold voltage (VTP) of the PMOS capacitor.
Therefore, a PLL used by the conventional loop filters has limited tuning range because the filters cannot output a precise or fine tuning voltage for controlling the local signal of the voltage controlled oscillator. A need therefore exists for a selection loop filter that occupies a small area and operates in the whole range of an electric source voltage.